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dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
uart
- 本程序的功能是实现串口通信，采用232传输协议，编码方式为8B/10B转换，即一位起始位，8位数据位，一位停止位，在actel Fusion系列开发板上得到验证，具有很强的通用性。本程序的编程语言为Verilog.-This procedure is to achieve the functions of serial communication, the transfer protocol is 232.The encoding protocol is 8B/10B , that is, a
clock
- 用verilog实现的数字钟，已经在ACTEL公司的A3P030的开发板上成功运行-Digital clock with Verilog , successfully ran on the board of ACTEL A3P030
111
- Verilog语言编写的循环彩灯控制器 这个程序我已经在Actel板上烧过了，没问题。如果还有什么问题应该是你的板不同或者工具不同，我是在libero_8.5上做的 -VeriloG HDL IS VEVRY USEFUL
TemperatureMonitor_lab
- 实现温度的实时的检测，使用Verilog语言，适用于actel公司的FPGA-To achieve real-time temperature detection, the use of Verilog language, the company' s FPGA for actel
hdl
- ACTEL FPGA 6位数码管计数999999，Verilog描述-ACTEL FPGA 6 bits digital tube count 999999, Verilog descr iption
Compare_4bit_74hc85
- ACTEL FPGA 74HC85实例演示，Verilog描述-ACTEL FPGA 74HC85 examples demonstrate, Verilog descr iption
74hc4017
- 实现的是扭环形十进制计数器，用verilog HDL 语言，在Actel公司提供的LiberoFPGA开发环境下实现，代码经过验证，可在ModelSim中仿真 -Ring is twisted to achieve a decimal counter, using verilog HDL language, Actel offers the LiberoFPGA development environment, the code is validated, the simulation in t
DFF
- actel fpga D触发器 verilog描述-pdf actel fpga d
adder
- actel fpga加法器的verilog源码，在libero环境开发的-actel fpga adder verilog source code, development environment in the libero
Syn_FIFO
- 基于Actel公司的开发平台，verilog实现同步fifo设计-Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
Static-PLL
- 基于Actel开发平台的静态锁相环设计，verilog实现-Actel development platform based on the static PLL design, verilog realized
Actel_DirectCore_CORESPI_4.2.116
- Actel DirectCore CORESPI 4.2.116 Verilog and VHDL RTL source files for SPI controller on APB
VerilogUart
- UART 串口通信模块，Verilog 实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-UART serial communication module, Verilog implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
bldc_motor_control_design_example
- 无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA- actel VERILOG BLDC control of the use of actel FPGA